This invention relates to semiconductor integrated circuit devices. The invention finds particular application in memories with logic functions for buffer storage and memory devices of a computer and will be described in conjunction therewith.
Heretofore, digital processors of computers and the like have included buffer storage that has memories with logic functions. The memories, typically random access memories (RAMs), have included a plurality of macrocells and a gate array. One such memory is disclosed in U.S. Pat. No. 4,959,704, issued Sep. 25, 1990 to Isomura, et al.
Because the prior art memories were constructed of bipolar transistors, it was difficult to achieve higher integration density and larger storage capacities. Moreover, the prior art memories were relatively power consumptive.
In order to cope with these difficulties, the inventors constructed a hybrid bipolar-CMOS type RAM. This hybrid RAM operated at a comparatively high speed, was capable of higher integration density, and consumed less power. However, even the hybrid memory had several drawbacks.
First, in the hybrid memory, the logic circuits, such as sequence control ,circuits, for selectively transmitting the output signals of the RAM macrocells were constructed by combining a plurality of unit gate array cells in a gate array portion. As the storage capacity of the hybrid memory was enlarged, the number of bits of storage input to and output from the RAM macrocells increased. To accommodate the increased data input and output, the number of spanning wiring lines between each RAM macrocell and the gate array portion increased and the transmission paths of the storage data items were lengthened. As a result, the layout design of the memory with logic functions became difficult to enlarge, and the operating speed of the memory was limited.
Second, the plurality of unit gate array cells of the gate array portion were connected with a supply voltage and ground through a supply voltage and ground feed wiring lines. As the scale of the hybrid memory was enlarged and the number of cells of the gate array portion increased, the fluctuation of the supply voltage within the gate array portion increased, rendering the operation of this portion unstable.
Third, the hybrid memory had some signals transmitted at ECL levels, (e.g. clock signals) and some signals transmitted at MOS levels (e.g. address signals). As the hybrid memory was microfabricated and the scale was enlarged, the mutual interference between these signals and the skew between bits increased, rendering its operation unstable.
Fourth, in the hybrid memory, signal wiring lines for the RAM macrocells were chiefly laid out by hand labor. The signal wiring lines for the gate array portion were chiefly laid out by automatic computer controlled machinery as the scale of the memory was enlarged, the number of the spanning wiring lines between the RAM macrocells and the gate array portion increased. It became difficult to lay out these spanning wiring lines in part manually and in part by automation.
Fifth, differential transistors were used in current switch circuits of high sensitivity. These current switch circuits and a bipolar-CMOS hybrid circuit were fed with the supply voltage through a common supply voltage feed point. A substrate potential pulling-up power source line, included in the bipolar-CMOS hybrid circuit, was coupled to that supply voltage feed wiring line of the current switch circuit side on which the supply voltage fluctuates comparatively little. Even when supply voltage feed wiring lines were laid separately for the current switch circuits and the bipolar-CMOS hybrid circuit, the source line was laid near N-channel MOSFETs. The operation of the memory with logic functions became unstable. The N-channel MOSFETs were reverse-biased to prevent latch-up.
The present invention solves the aforementioned several problems by stabilizing operation, providing an efficient layout design, and reducing the chip area.